1. Field of the Invention
The present invention relates to a method and an apparatus for interleaving/deinterleaving transmission/reception data in bit units in the field of information communication.
2. Prior Art
Conventionally, an interleaving apparatus interleaved data in word units, since data was read from storage means in word units. However, when a burst error occurred, interleaving in word units had a defect of causing many errors in one word.
Hence, an apparatus for interleaving data in bit units has been proposed in Japanese Patent No. 2999101 (Japanese Laid-open Patent Application No. Hei 07-049779). This interleaving apparatus sequentially reads data elements before interleaving, interleaves the data, carries out a logical operation of the data and the data (interleaving intermediate data in the middle of the processing) stored in the storage area, in which interleaved data is to be stored, of the storage means, and then stores the interleaved data at the same address of the storage means. The interleaving apparatus carries out the above-mentioned processing, thereby attaining interleaving. The interleaving apparatus described in Japanese Patent No. 2999101 (Japanese Laid-open Patent Application No. Hei 07-049779) is hereafter taken as a conventional example, and its configuration and operation will be described in detail below by using FIGS. 13 and 14.
FIG. 13 is a schematic diagram showing the interleaving apparatus in accordance with the conventional example. Numeral 10 designates data storage means, numeral 20 designates access information supply means, numeral 30 designates a first pointer, numeral 60 designates a third pointer, numeral 200 designates a multiplexer, numeral 210 designates logical operation means, numeral 220 designates a 1-bit shifter, numeral 230 designates a register, numeral 240 designates a latch, and numeral 250 designates control means.
The reception data stored in the data storage means 10 is read in word units by the first pointer 30 in accordance with the sequence of addresses and stored in r1 of the register 230. At that time, the data element in the most significant bit is stored in the latch 240.
The access information supply means 20 stores address information and bit position information, respectively regarding addresses and bits in which interleaved data elements are stored, in address storage means 21 in accordance with the sequence of addresses obtained before interleaving. The address information is output to the third pointer 60, and 1-word data is read from the address designated by the third pointer 60. The bit position information is output to the control means 250. When the data element stored in the latch 240 is 0, the control means 250 outputs 1-word data wherein the value in the bit position designated by the bit position information is 0 and the values at the other bit positions are 1. The logical operation means 210 computes the AND of the 1-word data of the control means 250 with the 1-word data read from the address designated by the third pointer 60 and stores the AND in r0. On the other hand, when the data element stored in the latch 240 is 1, the control means 250 outputs 1-word data wherein the value in the bit position designated by the bit position information is 1 and the values at the other bits are 0. The logical operation means 210 computes the OR of the 1-word data of the control means 250 with the 1-word data read from the address designated by the third pointer 60 and stores the OR in r0. The data stored in r0 is written in the data storage means 10. Hence, among the data elements in the 1-word data stored at the address designated by the third pointer 60, only the data element in the bit corresponding to the bit position information is rewritten to the data element stored in the latch 240, whereby the data in the data storage means 10 is overwritten.
Then, the data in r1 is shifted to higher-order bits by one bit and stored again in r1, and the data element in the most significant bit is stored in the latch 240. The above-mentioned procedure is repeated. When the procedure is completed for all the data elements of the 1-word data stored in r1, 1-word data is read again from the address designated by the first pointer 30, and the above-mentioned procedure is repeated. Interleaving ends when the procedure is completed for all the reception data.
FIG. 14 is a table illustrating a program in accordance with the conventional example. At step 0, the address information supplied by the access information supply means 20 is set in the third pointer 60. At step 1, the 1-word data at the address designated by the first pointer 30 is stored in r1, the data element in the most significant bit is stored in the latch 240, and the first pointer 30 is incremented by one. At step 2, the number of repetitions is set at a number so that the processing is repeated by the number corresponding to the bit width of one word. At step 3, the 1-word data stored at the address, designated by the third pointer 60, of the data storage means 10 is read, the data element held in the latch 240 is set in the bit position designated by the bit position information, and the obtained data is stored in r0, and a second pointer 22 is incremented by one. At step 4, the 1-word data in r0 is transferred to the address, designated by the third pointer 60, of the data storage means 10. At step 5, the data in r1 is shifted to higher-order bits by one bit and stored in r1. The data element in the most significant bit is stored in the latch 240, the next address information is set in the third pointer 60. If the number of repetitions is not more than the preset number, the procedure returns to step 3. If the number of repetitions is more than the preset number, step 6 is then carried out. At step 6, if interleaving has not been carried out for all the data elements, the procedure returns to step 1. If interleaving has been carried out, the program ends. The program comprises the above-mentioned processing steps.
Deinterleaving is carried out in accordance with a procedure similar to that described above, since deinterleaving is different from interleaving only in the address information and the bit position information stored in the address storage means 21.
However, in the conventional example, the addresses and bit positions, in which interleaved data elements are stored, of the data storage means 10 are not continuous. Hence, in order to store one data element, it is necessary to carry out a logical operation with the interleaving intermediate data at the address of the storage destination. In addition, the processing by the logical operation means 210 must be switched depending on whether the data element is 0 or 1. This has a problem of making the size of the circuit larger and making the logical operation more complicated. Furthermore, it is necessary to write 1-word data in the data storage means 10 each time 1-bit data is interleaved. This has a problem of increasing the number of processing steps and the number of the total processing steps of the program.
Moreover, problems similar to those described above occur in the case of deinterleaving, since deinterleaving is different from interleaving only in the address information and the bit position information stored in the address storage means 21.
Still further, in order that selection is made between interleaving and deinterleaving in the conventional example, there is a problem of requiring that the address information and the bit position information are rewritten.